The present invention relates to BICMOS voltage reference circuits, and in particular to such reference circuits for EPROMs.
A typical prior art positive voltage reference is shown in FIG. 1. The voltage reference is provided on a line 10 from a bipolar transistor 12 which is coupled to a positive voltage supply VCC. A current source 14 provides the necessary current. Transistor 12 is biased by a resistor 16 coupled to voltage supply VCC. A second current source 18 provides the appropriate current to the base of transistor 12 to provide the appropriate voltage level at reference line 10.
FIG. 2 shows a typical use for such a reference generator circuit 20 for an ECL memory. Reference line 10 is connected through resistors 22 in row decode circuits 24 to row lines 0, 1 and 2, respectively. As can be seen, with a large number of row lines connected, the circuit of FIG. 1 will reach the maximum amount of current of current source 14 and thus pull down the voltage at reference line 10. This phenomena is shown in FIG. 3 during a switching period 26 in which a row line 1 goes high but a row line 0 has not yet discharged, causing the reference line to give a false indication of a high value on row line 2. If the current source 14 in FIG. 1 is split among enough row lines, the amount of current to each row line will decrease, thus increasing the amount of time required to discharge the row lines. Without sufficient current to quickly discharge a deselected row, the speed of the address access is slowed.
One solution is to add a discharge circuit to discharge the capacitance of a row line and thus limit the amount of current required from the voltage reference circuit. However, this adds a considerable amount of circuitry since a separate discharge circuit is required for each row line. Such a discharge circuit is shown on page 108-109 of the 1983 IEEE International Solid-State Circuits Conference Digest of Technical Papers.